Design of a fault tolerant 100 Gbits solid-state mass memory for satellites

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 281-286

  Kluth, M P ^a   Simon, F ^a   Le Gall, J Y ^a   Muller, E ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; SATELLITES; SEMICONDUCTOR DEVICE TESTING; SOLID STATE DEVICES; SPACE APPLICATIONS; SPACECRAFT EQUIPMENT; VLSI CIRCUITS;

MEMORY CARDS; MEMORY MANAGEMENT; SOLID STATE MASS MEMORY;

SEMICONDUCTOR STORAGE;

EID: 0029701222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)