Design of a 20-Mb/s 256-state Viterbi decoder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 6, 2003, Pages 965-975

  Liu, Xun ^a   Papaefthymiou, Marios C ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Bus reduction; Communications; Data transfer; Low power; Pipelining

Indexed keywords

DATA COMMUNICATION EQUIPMENT; DATA TRANSFER; DECODING; DESIGN FOR TESTABILITY; DIGITAL ARITHMETIC; INTERCONNECTION NETWORKS;

REGISTER TRANSFER LEVEL; SATURATION ARITHMETIC; VITERBI DECODER;

VLSI CIRCUITS;

EID: 0742284471     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.817547     Document Type: Article

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