Trellis pipeline-interleaving: A novel method for efficient viterbi-decoder implementation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1992, Pages 1875-1878

  Dawid, Herbert ^a   Bitterlich, Stefan ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINES;

ACHIEVABLE THROUGHPUTS; COMMUNICATION PROBLEMS; HIGH SPEED IMPLEMENTATION; LOOSELY COUPLED; NUMBER OF STATE; SPECIFIC PROPERTIES; TRELLIS DIAGRAM; VITERBI DECODER;

VITERBI ALGORITHM;

EID: 84888049999     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230446     Document Type: Conference Paper

References (10)

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