2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 6, 2000, Pages 826-834

  Chang, Yun Nan ^a,b   Suzuki, Hiroshi ^a,c,d   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^c JFE STEEL CORPORATION   (Japan)

^d UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; DATA STORAGE EQUIPMENT; DECODING; LOGIC CIRCUITS; LOGIC DESIGN; MULTIPLYING CIRCUITS;

ADD COMPARE SELECT MODULE; BIT SERIAL MULTIPLIER; POWER DISSIPATION; TIME MULTIPLEXING METHOD; VITERBI DECODER;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 0033703263     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.845186     Document Type: Article

References (20)

1. G. D. Jorney Jr., "The Viterbi algorithm," Proc. IEEE, vol. 61, pp. 268-278, Mar. 1973.
2. P. J. Black and T. H. Meng, "A 140-Mb/s, 32-state, radix-4 Viterbi decoder," IEEE J. Solid-State Circuits, vol. 27, pp. 1877-1885, Dec. 1992.
3. A. K. Yeung and J. Rabaey, "A 210-Mb/s, radix-4 bit-lexel pipelined Viterbi decoder," ISSCC Dig. Tech. Papers, pp. 88-89, Feb. 1995.
4. J. K. Hinderling et al., "CDMA mobile station modem ASIC," IEEE J. Solid-State Circuits, vol. 28, pp. 253-260, Mar. 1993.
5. I. Kang and A. N. Willson, Jr., "Low-power Viterbi decoder for CDMA mobile terminals," IEEE J. Solid-State Circuits, vol. 33, pp. 473-482, Mar. 1998.
6. G. Fettweis and H. Meyr, "Feedforward architecture for parallel Viterbi decoding," J. VLSI Signal Processing, vol. 3, pp. 105-119, 1991.
7. K. K. Parhi, "High-speed VLSI architectures for Huffman and Viterbi decoders," IEEE Trans. Circuits Syst. II, vol. 39, pp. 385-391, June 1992.
8. H. D. Lin and D. G. Messerschmitt, "Algorithm and architectures for concurrent Viterbi decoding," in Proc. ICC'89, vol. 2, June 1989, pp. 836-840.
9. "Japan's proposal for candidate radio transmission technology IMT-2000: W-CDMA," in Association of Radio Industries and Businesses (ARIB). Japan, June 1998.
10. C. M. Rader, "Memory management in a Viterbi decoder," IEEE Trans. Commun., vol. 29, pp. 1399-1401, Sept. 1981.
11. R. Cyper and C. B. Shung, "Generalized trace-back techniques for survivor memory management in the Viterbi algorithm," Proc. GLOBECOM, vol. 2, pp. 1318-1322, Dec. 1990.
12. H.A. Bustamente et al., "Stanford telecom VLSI design of convolutional decoder," Proc. MILCOM, vol. 1, pp. 171-178, Oct. 1989.
13. G. Feygin and P. G. Gulak, "Architectural tradeoffs for survivor sequence memory management in Viterbi decoders," IEEE Trans. Commun., vol. 41, pp. 425-429, Mar. 1993.
14. H. Suzuki, Y.-N. Chang, and K. K. Parhi, "Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems," in IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1999, pp. 589-592.
15. H. Dawid, S. Bitterlich, and H. Meyr, "Trellis pipeline-interleaving: A novel method for efficient Viterbi decoder implementation," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, San Diego, CA, May 1992, pp. 1875-1878.
16. J. Sparso, H. N. Jorgensen, E. Paaske, S. Pedersen, and T. Rubner-Petersen, "An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures," IEEE J. Solid-State Circuits, vol. 26, pp. 90-96, Feb. 1991.
17. H.-L. Lou, "Implementing the Viterbi algorithm, fundamentals and real-time issues for processor designers," IEEE Signal Processing Mag., vol. 12, pp. 42-52, Sept. 1995.
18. C. B. Shung, P. H. Siegel, G. Ungerboeck, and H. K. Thaper, "VLSI architecture for metric normalization in the Viterbi algorithm," in Int. Conf. Communications, vol. 4, Atlanta, GA, Apr. 1990, pp. 1723-1728.
19. C. J. Nicol et al., "A low-power 128-tap digital adaptive equalizer for broadband modems," IEEE J. Solid-State Circuits, vol. 32, pp. 1777-1789, Nov. 1997.
20. C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time-power tradeoffs in parallel adders," IEEE Trans. Circuits Syst. II, vol. 43, pp. 689-702, Oct. 1996.