550 Mb/s radix-4 bit-level pipelined 16-state 0.25-μm CMOS viterbi decoder

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2000, Pages 195-201

  Gierenz, V S ^a   Weiss, O ^a   Noll, T G ^a   Carew, I ^a   Ashley, J ^a   Karabed, R ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; DECODING; LOGIC GATES; MAGNETIC DISK STORAGE; MAXIMUM LIKELIHOOD ESTIMATION; PIPELINE PROCESSING SYSTEMS;

MAXIMUM LIKELIHOOD SEQUENCE DETECTION; VITERBI DECODER;

DIGITAL SIGNAL PROCESSING;

EID: 0033712751     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)