Partitioning programming environment for a novel parallel architecture

IEEE Symposium on Parallel and Distributed Processing - Proceedings

Volumn , Issue , 1996, Pages 544-548

  Hartenstein, R ^a   Becker, J ^a   Herz, M ^a   Kress, R ^a   Nageldinger, U ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; PROGRAM COMPILERS;

PARALLEL ARCHITECTURE; PARTITIONING PROGRAMMING ENVIRONMENT; RECONFIGURABLE DATAPATH HARDWARE; UNIVERSAL EMBEDDED ACCELERATOR;

COMPUTER SYSTEMS PROGRAMMING;

EID: 0029718320     PISSN: 10636374     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)