Scaling and folding the viterbi algorithm trellis

Workshop on VLSI Signal Processing 1992

Volumn , Issue , 1992, Pages 479-489

  Chau, Paul M ^a   Stephen, Karen J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; GEOMETRY; MEMORY ARCHITECTURE; SIGNAL PROCESSING; SYSTEMS ANALYSIS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

CODE PARAMETERS; CUBE-CONNECTED CYCLES; HARDWARE IMPLEMENTATIONS; PARALLEL HARDWARE; PROCESSING ELEMENTS; SINGLE PROCESSORS; VITERBI DECODER; VLSI ARCHITECTURES;

VITERBI ALGORITHM;

EID: 11644294247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISP.1992.641079     Document Type: Conference Paper

References (10)

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2. H.-D. Lin, C. B. Shung, D. G. Messerschmidt, "Folded Viterbi Decoders for Convolutional Codes, " in VLSI Signal Processing IV. New York: IEEE Press, 1990, pp. 381-391.
3. F. P. Preparata and J. Vuillemin, "The Cube-Connected Cycles: A Versatile Network for Parallel Computation, " Communications of the ACM, vol. 24, no. 5, pp. 300-309, May 1981.
4. P. G. Gulak and E. Shwedyk, "VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications, " IEEE Journal on Selected Areas in Communications, SAC-4, no. 1, pp. 142-154, Jan. 1986.
5. P. G. Gulak and T. Kailath, "Locally Connected VLSI Architectures for the Viterbi Algorithm, " IEEE Journal on Selected Areas in Communications, SAC-6, no. 3, pp. 527-537, April 1988.
6. W.-T. Lin and C.-Y. Ho, "A New FFT Mapping Algorithm for Reducing the Traffic in a Processor Array, " in VLSI Signal Processing II. New York: IEEE Press, 1986, pp. 328-335.
7. H.-D. Lin and D. G. Messerschmidt, "Algorithms and Architectures for Concurrent Viterbi Decoding, " in Proceedings of the International Conference on Communications, Boston, June 1989.
8. C. D. Thompson, "Fourier Transforms in VLSI, " IEEE Transactions on Computers, CT-32, no. 11, pp. 1047-1057, April 1988.
9. A. P. Hekstra, "An Alternative to Metric Rescaling in Viterbi Decoders, " IEEE Transactions on Communications, vol. 37, no. 11, pp. 1220-1222, Nov. 1989.
10. C. B. Shung, P. H. Siegel, G. Ungerboeck, H. K. Thapar, "VLSI Architectures for Metric Normalization in the Viterbi Algorithm, " in IEEE International Conference on Communications, April 1990, pp. 1723-1728.