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Volumn 2, Issue , 1990, Pages 1323-1327
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A Viterbi decoder architecture based on parallel processing elements
a
a
SIEMENS AG
(Germany)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SYSTEMS, DIGITAL--PARALLEL PROCESSING;
DIGITAL COMMUNICATION SYSTEMS;
INTEGRATED CIRCUITS, VLSI;
RADIO SYSTEMS;
SIGNAL PROCESSING;
CONVOLUTIONAL CODES;
DIGITAL RADIO;
RAM MACROS;
TRELLIS CODES;
VITERBI DECODERS;
VLSI CHIPS;
CODES, SYMBOLIC;
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EID: 0025555832
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (2)
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References (10)
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