210 Mb/s radix-4 bit-level pipelined Viterbi decoder

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Yeung, Alfred K ^a   Rabaey, Jan M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; PIPELINE PROCESSING SYSTEMS;

ADD COMPARE SELECT (ACS) UNITS; CARRY PROPAGATION FREE ADDITION; REDUNDANT NUMBER REPRESENTATION; VITERBI DECODER;

DECODING;

EID: 0029252075     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)