Automatic generation of critical-path tests for a partial-scan microprocessor

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 180-186

  Grodstein, Joel ^a   Bhavsar, Dilip ^a   Bettada, Vijay ^a   Davies, Richard ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CROSSTALK; DELAY CIRCUITS; DESIGN FOR TESTABILITY; STATISTICAL METHODS; SWITCHING CIRCUITS;

AUTOMATIC TEST PATTERN GENERATOR; CRITICAL PATH TEST; PARTIAL SCAN MICROPROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0344119472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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