Pitfalls in delay fault testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 3, 1997, Pages 321-329

  Pierzynska, Alicja ^a   Pilarski, Slawomir ^a  

^a SIMON FRASER UNIVERSITY   (Canada)

Author keywords

Delay effects; Delay estimation; Design for testability; Fault modeling (new)

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SOFTWARE; ELECTRIC FAULT CURRENTS; ESTIMATION; INTEGRATED CIRCUIT TESTING; LOGIC GATES; SEMICONDUCTOR DEVICE MODELS;

DELAY EFFECTS; SOFTWARE PACKAGE SPICE;

VLSI CIRCUITS;

EID: 0031102315     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.594838     Document Type: Article

References (31)

1. J.L. Carter, V. S. Iyengar, and B. K. Rosen, "Efficient test coverage determination for delay faults," in Proc. Int. Test Conf., Sept. 1987, pp. 418-427.
2. J. Savir, "Skewed-load transition test: Part I, calculus," in Proc. Int. Test Conf., Sept. 1992, pp. 705-713.
3. S. Paul and J. Savir, "Skewed-load transition test: Part II, coverage," in Proc. Int. Test Conf., Sept. 1992, pp. 714-722.
4. A.K. Pramanick and S. M. Reddy, "On detection of delay faults," in Proc. Int. Test Conf., Sept. 1988, pp. 845-856.
5. V.S. Iyengar, B. K. Rosen, and J. A. Waicukauski, "On computing the sizes of detected delay faults," IEEE Trans. Computer-Aided Design, vol. 9, pp. 299-312, Mar. 1990.
6. G.L. Smith, "Model for delay faults based upon paths," in Proc. Int. Test Conf., Nov. 1985, pp. 342-349.
7. A. Krasniewski and L. Wronski, "Coverage of delay faults: When 13% and 99% mean the same," in Lecture Notes in Computing Science: Dependable Computing, vol. 852, K. Echtle, D. Hammer, and D. Powell, Eds. Berlin: Springer Verlag, 1994, pp. 178-195.
8. C.J. Lin and S. M. Reddy, "On delay fault testing in logic circuits," in Proc. Int. Conf. Computer-Aided Design, Nov. 1986, pp. 148-151.
9. K.T. Cheng and H. C. Chen, "Delay testing for nonrobust untestable circuits," in Proc. Int. Test Conf., Oct. 1993, pp. 954-961.
10. E.S. Park and M. R. Mercer, "An efficient delay test generation system for combinational logic circuits," IEEE Trans. Computer-Aided Design, vol. 11, pp. 926-938, July 1992.
11. W. Mao and M.D. Ciletti, "Robustness enhancement and detection threshold reduction in ATPG for gate delay faults," in Proc. Int. Test Conf.. Sept. 1992, pp. 588-596.
12. C.J. Lin and S. M. Reddy, "On delay fault testing in logic circuits," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 694-703, Sept. 1987.
13. S. Paul and S. Reddy, "A test generation system for path delay faults," in Proc. IEEE Int. Conf. Computer Design. Oct. 1989, pp. 40-43.
14. P.C. McGeer, A. Saldanha, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Timing analysis and delay-fault test generation using path-recursive functions," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 180-183.
15. S.T. Chakradhar, M. A. Iyer, and V. D. Agrawal, "Energy minimization based delay testing," in Proc. European Design Automation Conf., Sept. 1992, pp. 280-284.
16. I. Pomeranz and S.M. Reddy, "Test generation for path delay faults based on learning," in Proc. Int. Conf. Computer-Aided Design, 1993, pp. 428-435.
17. "NEST: A nonenumerative test generation method for path delay faults in combinational circuits," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1505-1515, Dec. 1995.
18. K. Roy, J.A. Abraham, K. De, and S. Lusky, "Synthesis of delay fault testable combinational logic," in Proc. Int. Conf. Computer-Aided Design, Nov. 1989, pp. 418-421.
19. S. Devadas and K. Keutzer, "Synthesis of robust delay-fault-testable circuits: Theory," IEEE Trans. Computer-Aided Design, vol. 11, pp. 87-101, Jan. 1992.
20. "Synthesis of robust delay-fault-testable circuits: Practice," IEEE Trans. Computer-Aided Design, vol. 11, pp. 277-300, Mar. 1992.
21. N.K. Jha, I. Pomeranz, S. M. Reddy, and R. J. Miller, "Synthesis of multi-level combinational circuits for complete robust path delay fault testability," in Proc. Fault-Tolerant Computing Symp., July 1992, pp. 280-287.
22. X. Xie, A. Albicki, and A. Krasniewski, "Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion," in Proc. IEEE Int. Conf. Computer Design, Oct. 1992, pp. 482-485.
23. A. El-Maleh and J. Rajski, "Delay-fault testability preservation of the concurrent decomposition and factorization transformations," in Proc. IEEE VLSI Test Symp., 1994, pp. 15-21.
24. P. Franco and E.J. McCluskey, "Three-pattern tests for delay faults," in Proc. IEEE VLSI Test Symp., Apr. 1994, pp. 452-456.
25. A. Pierzynska and S. Pilarski, "Timing issues in delay fault testing," Simon Fraser University, Burnaby, B.C., Canada, Tech. Rep. CSS/LCCR TR94-03, Apr. 1994.
26. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1985.
27. S.M. Reddy and M. K. Reddy, "Testable realizations for FET stuck-open faults in CMOS combinational logic circuits," IEEE Trans. Comput., vol. C-35, pp. 742-754, Aug. 1986.
28. J. Savir and S. Patil, "Broad side delay test," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1057-1064, Aug. 1994.
29. A. Pierzynska and S. Pilarski, "Pitfalls in delay fault testing," Simon Fraser University, Burnaby, B.C., Canada, Tech. Rep. CSS/LCCR TR95-05, Feb. 1995.
30. "Quality considerations in delay fault testing," in Proc. European Design Automation Conf., Sept. 1995, pp. 196-201.
31. "Non-robust versus robust," in Proc. Int. Test Conf., Oct. 1995, pp. 123-131.