Scan Islands - A scan partitioning architecture and its implementation on the Alpha 21364 processor

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 16-21

  Bhavsar, D K ^a   Davies, R A ^b  

^a INTEL CORPORATION   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

Automatic control; Automatic test pattern generation; Centralized control; Circuit testing; Computer aided manufacturing; Computer architecture; High performance computing; Microprocessors; Pins; Very large scale integration

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; AUTOMATION; COMPUTER AIDED MANUFACTURING; COMPUTER TESTING; CONTROL; INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; MANUFACTURE; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

CENTRALIZED CONTROL; CIRCUIT TESTING; HIGH PERFORMANCE COMPUTING; MANUFACTURING TESTS; PINS; SCAN DESIGNS; SCAN PARTITIONING; TEST DEVELOPMENT;

COMPUTER ARCHITECTURE;

EID: 79957543174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011105     Document Type: Conference Paper

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