Optimal time expansion model based on combinational ATPG for RT level circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 190-197

  Inoue, Tomoo ^a   Hosokawa, Toshinori ^a   Mihara, Takahiro ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATORS (ATPG);

COMPUTER AIDED LOGIC DESIGN; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

SEQUENTIAL CIRCUITS;

EID: 0032294839     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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