Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 384-390

  Paul, Bipul C ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC NETWORK SYNTHESIS; VECTORS;

AUTOMATIC TEST PATTERN GENERATION; DYNAMIC TIMING ANALYSIS; SOFTWARE PACKAGE HSPICE;

INTEGRATED CIRCUIT TESTING;

EID: 0036446483     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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