Crosstalk test generation on pseudo industrial circuits: A case study

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 548-557

  Chen, Liang Chi ^a   Mak, T M ^a   Breuer, Melvin A ^a   Gupta, Sandeep K ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MICROPROCESSOR CHIPS; SIGNAL RECEIVERS;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

CROSSTALK;

EID: 0035687656     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. Analytic models for crosstalk delay and pulse analysis under non-ideal inputs
2. Test generation in VLSI circuits for crosstalk noise
3. Test generation for crosstalk-induced delay in integrated circuits
4. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
5. An implicit enumeration algorithm to generate tests for combinational logic circuits
6. RICE: Rapid interconnect circuit evaluation using AWE
7. A new framework for static timing analysis, incremental timing analysis, and timing simulation
8. On the acceleration of test generation algorithms
9. On necessary and nonconflicting assignments in algorithmic test pattern generation
10. Static logic implication with application to redundancy identification
11. Advanced automatic test pattern generation and redundancy identification techniques
12. Fast identification of untestable delay faults using implications
13. TACO: Timing analysis with coupling
14. Switching window computation for static timing analysis in presence of crosstalk noise
15. FANHAT: Fanout oriented hierarchical automatic test generation system
16. Multiple path sensitization for hierarchical circuit testing
17. High quality robust tests for path delay faults
18. Switch-level delay test
19. A new gate delay model for simultaneous switching and its applications
20. Test generation and three-state elements, busses, and bidirectionals
21. Compact test sets for industrial circuits
22. Gate-level test generation for sequential circuits: A survey