Realistic delay modeling in satisfiability-based timing analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1998, Pages 215-218

  Guerra e Silva, Luis ^a   Marques Silva, Joao P ^a   Silveira, Luis Miguel ^a   Sakallah, Karem A ^a  

^a INESC   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; MATHEMATICAL MODELS;

CIRCUIT DELAYS; PATH SENSITIZATION; TIMING ANALYSIS;

ELECTRIC NETWORK ANALYSIS;

EID: 0031630285     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)