Combinational test generation for various classes of acyclic sequential circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1078-1087

  Kim, Yong Chang ^a   Agrawal, Vishwani D ^a   Saluja, Kewal K ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER HARDWARE; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS;

ACYCLIC SEQUENTIAL CIRCUITS; BALANCED CIRCUITS; COMBINATIONAL TEST GENERATION;

SEQUENTIAL CIRCUITS;

EID: 0035680983     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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7. Theorems for separable primary input faults in internally balanced structures
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9. An analytical approach to the partial scan problem
10. A test methodology for finite state machines using partial scan design
11. i: A test generation package for sequential circuits
12. Paritial scan design methods based on internally balanced structure