An extended class of sequential circuits with combinational test generation complexity

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 200-205

  Inoue, Michiko ^a   Jinno, Chikateru ^a,b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; MATHEMATICAL TRANSFORMATIONS; SEQUENTIAL CIRCUITS; SHIFT REGISTERS; THEOREM PROVING;

COMBINATIONAL TEST GENERATION COMPLEXITY; EXTENDED COMBINATORIAL TRANSFORMATION; INTERNALLY SWITCHED BALANCED STRUCTURE;

DESIGN FOR TESTABILITY;

EID: 0036395447     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106770     Document Type: Article

References (12)

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