Library-Based Process Test Vehicle Design Framework

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5042, Issue , 2003, Pages 188-196

  Doong, Kelvin Y Y ^a   Hung, L J ^a   Ho, Susan ^a   Lin, S C ^a   Young, K L ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Electronic design automation; Logic process; Migration; SoC; Synthesis; Test structure; Test vehicle

Indexed keywords

AUTOMATION; INTEGRATED CIRCUITS; LOGIC DEVICES; VEHICLES;

PROCESS PARAMETER EXTRACTION;

MICROPROCESSOR CHIPS;

EID: 0242525077     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485264     Document Type: Conference Paper

References (19)

1. W. Lukaszek, K. G. Grambow, and W. J. Tarbrough, "Test vehicle based approach to automated diagnosis of CMOS yield problems", IEEE Trans. Semiconductor Manufacturing, Vol. 3, pp. 18-27, Feb., 1990.
2. C. Weber, "Generic test chip formats for ASIC-oriented semiconductor process development", Proc. IEEE Int. Conf. Microelectronic Test Structures, pp. 247 -252, 1993
3. Crid Yu, T. Maung, C. J. Spanos, D. S. Boning, J. E. Chung, H.Y. Liu, K.J. Chang, D. J. Bartelink, "Use of short-loop electrical measurements for yield improvement" IEEE trans. on semiconductor manufacturing, Vol. 8, No. 2, pp. 150-159, May, 1995
4. K. Y.-Y. Doong, S. Hsieh, S.-C. Lin, M.-H. Lee, C.-W. Huang, J.-Y. Cheng, Y.-H. Yang, K. Miyamoto, and C. C.-H. Hsu, "A novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure site test structures", Proc IEEE Int. Symp. Semiconductor Manufacturing (ISSM), pp. 241 - 244, Oct. 1999
5. K. Miyamoto, K. Inoue, I. Tamura, N. Kondo, H. Inoto, I.I. Ito, K. Kasahara, and Y. Oshikiri, "Yield management methodology for SoC vertical yield ramp", Proc. Int. Electron Device Meeting, 2000
6. M. T. Bohr and Y. A. El-Mansy, "Technology for advanced high-performance microprocessors", IEEE Trans. Electron Devices, Vol. 45, No. 3, pp. 620 -625, March, 1998
7. C. Hess, B.E. Stine, L.H. Weiland, and K. Sawada, "Logic Characterization Vehicle to Determine Process Variation Impact on Yield and Performance of Digital Circuits", Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 189-196, April, 2002
8. M.V. Kumar, W. Lukaszek, and J. D. Plummer, "A test structure advisor and a coupled, library-based test structure layout and testing environment", IEEE Trans. Semiconductor Manufacturing, Vol. 10 Issue: 3, pp. 370 -383, Aug., 1997
9. L. Kasel, C.C. McAndrew, P. Drennan, W. F. Davis, and R. Ida, "Automated generation of SPICE characterization test masks and test databases", Proc. IEEE Int. Conf. Microelectronic Test Structures, pp. 74 -79. 1999
10. Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, "Automatic layout recycling based on layout description and linear programming", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15 No. 8, pp. 959 - 967, Aug. 1996
11. Antun Domic, Digital Equipment Corporation, Hudson, "Layout Synthesis of MOS Digital Cells", Proc. of Design Automation Conf., pp. 241-245, 1990
12. D. A. Bensouiah, R. J. Mack, and R. E. Massara, "Analog Layout Generation: from Design Assistant to Automated Layout", Proc. 40th Midwest Symposium on Circuits and Systems, Vol. 2, pp. 1038 - 1041, 1997
13. H. Onodera, M. Hashimoto, and T. Hashimoto, "ASIC design methodology with on-demand library generation", Digest of Technical Papers 2001 Symposium on VLSI Circuits, pp.57 -60, 2001
14. M. Dessouky, M.-M. Louerat, J. Porte, "Layout-oriented synthesis of high performance analog circuits", Proc. of Design, Automation and Test in Europe Conference, pp. 53 -57, 2000
15. R. Mandal, D. Goswami, and A. Dash, "Reducing library development cycle time through an optimum layout create now", Proc. Of ASP-DAC, pp. 655 -660, 2002
16. Silicon Canvas, "Laker ver. 3.0 TCL command reference", www. Sicanvas.com
17. K. Yoshida, T. Fujimaki, K. Miyamoto, T. Honma, H. Kaneko, H.Nakazawa, and M. Orita, "Stress-Induced voiding phenomena for an actual CMOS LSI interconnects", Technical Digest 2002 Inter. Electron Devices Meeting, 2002
18. Kelvin Y.-Y. Doong, R.C.J. Wang, S.-C. Lin, L.J. Huang, S.Y. Lee, C.C. Chiu, D.H. Su, K.L. Young, K. Wu, and Y.K. Peng, "Stressed-induced voiding and its geometry dependency characterization", to be published in, Proc. of Inter. Reliability Physical Symp., 2003
19. Kelvin Y.Y. Doong, Robin C. J. Wang, Jurcy C.H. Huang, L.J. Hung, S. Z. Lee, and K.L.Young, "Design and Integration of Electrical-based Dimensional Process-Window Checking Infrastructure", to be published in, Proc. IEEE Int. Conf. Microelectronic Test Structures, 2003