ASIC design methodology with on-demand library generation

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 57-60

  Onodera, H ^a   Hashimoto, M ^a   Hashimoto, T ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION; TUNING;

ON-DEMAND LIBRARY GENERATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0034795643     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Closing the gap between ASIC and custom: An ASIC perspective
2. C5M - A control-logic layout synthesis system for high-performance microprocessors
3. Library-less synthesis for static CMOS combinational logic circuits
4. Layout generation of primitive cells with variable driving strength
5. CELLERITY: A fully automatic layout synthesis system for standard cell libraries
6. An overview of library characterization in semi-custom design
7. Proposal of a timing model for CMOS logic gates driving a CRC π load
8. I developed a CPU in this way!
9. Vector quantization processor for mobile video communication
10. Post-layout transistor sizing for power reduction in cell-based design