A test structure advisor and a coupled, library-based test structure layout and testing environment

IEEE Transactions on Semiconductor Manufacturing

Volumn 10, Issue 3, 1997, Pages 370-383

  Kumar, Madan V ^b   Lukaszek, Wes ^c   Rummer, James D ^a,d  

^a IEEE   (United States)

^b HPL Technologies Inc   (United States)

^c Wafer Charging Monitors Inc   (United States)

^d Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER INTEGRATED MANUFACTURING; COMPUTER SOFTWARE; INTEGRATED CIRCUIT TESTING; THIN FILM TRANSISTORS;

TEST STRUCTURE ADVISOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031198443     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.618210     Document Type: Article

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