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Volumn , Issue , 2002, Pages 189-196

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTERFACES (COMPUTER); LOGIC CIRCUITS; MICROELECTRONIC PROCESSING; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS;

EID: 0037481688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (22)

References (6)
  • 1
    • 0037840074 scopus 로고
    • Microelectronic test chips for VLSI electronics
    • Chap.9, Academic Press
    • Buehler, M. G. Microelectronic Test Chips for VLSI Electronics VLSI Electronics Microstructure Science, pp. 529-576, Vol. 9, Chap.9, Academic Press, 1983
    • (1983) VLSI Electronics Microstructure Science , vol.9 , pp. 529-576
    • Buehler, M.G.1
  • 3
    • 0029304862 scopus 로고
    • Integrated circuit yield management and yield analysis: Development and implementation
    • Staper, C. H., Rosner, R. J. Integrated Circuit Yield Management and Yield Analysis: Development and Implementation IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995
    • (1995) IEEE Transactions on Semiconductor Manufacturing , vol.8 , Issue.2 , pp. 95-102
    • Staper, C.H.1    Rosner, R.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.