Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2002, Pages 189-196

  Hess, Christopher ^a   Stine, Brian E ^a   Weiland, Larg H ^a   Sawada, Kazuhiro ^b  

^a PDF SOLUTIONS INC   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTERFACES (COMPUTER); LOGIC CIRCUITS; MICROELECTRONIC PROCESSING; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS;

CHIPS FUNCTIONALITY; DESIGN OF EXPERIMENTS; LOGIC CHARACTERIZATION VEHICLE;

DIGITAL CIRCUITS;

EID: 0037481688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Buehler, M. G. Microelectronic Test Chips for VLSI Electronics VLSI Electronics Microstructure Science, pp. 529-576, Vol. 9, Chap.9, Academic Press, 1983
2. Daniel N. Maynard, Bette Bergman Reuter, Raymond J. Rosner SwampFinder Advanced Semiconductor Manufacturing Conference (ASMC), Munich, Germany, pp. 151-155, April 2001
3. Staper, C. H., Rosner, R. J. Integrated Circuit Yield Management and Yield Analysis: Development and Implementation IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995
4. Ciplickas, D. J., Li, X., Strojwas, A. J. Predictive Yield Modeling of VLSI's International Workshop on Statistical Metrology (IWSM), 2000
5. Hwang, K. Computer Arithmetic: Principles, Architecture and Design John Wiley & Sons, USA, 1979
6. Waser, S., Flynn, M. J. Introduction to Arithmetic for Digital System Designers CBS College Publishing, 1982