Yield management methodology for SoC vertical yield ramp

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 841-844

  Miyamoto, K ^a   Inoue, K ^a   Tamura, I ^a   Kondo, N ^a   Inoto, H ^a   Ito, I ^a   Kasahara, K ^a   Oshikiri, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; ELECTRONICS INDUSTRY; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

SYSTEM ON CHIP (SOC) TECHNOLOGY; VERTICAL YIELD RAMPS (VYR); YIELD MANAGEMENT TECHNOLOGY;

LSI CIRCUITS;

EID: 0034453902     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A novel assessment of process control monitor in advanced semiconductor manufacturing
2. Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure
3. Advanced yield learning through predictive micro-yield modeling