Reducing library development cycle time through an optimum layout create flow

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 655-660

  Mandal, R ^a   Goswami, D ^a   Dash, A ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN; ENGINES; SIMULATED ANNEALING;

AUTOMATIC LAYOUT GENERATION; DEFINITION PHASE; DEVELOPMENT CYCLE; INTEGRATED METHODOLOGY; LAYOUT GENERATIONS; LIBRARY GENERATION; MIGRATION FLOWS; OPTIMUM COMBINATION;

DIGITAL LIBRARIES;

EID: 0242719322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995010     Document Type: Conference Paper

References (9)

1. Sadiq M. Sait & Habib Youssef," VLSI PHYSICAL DESIGN AUTOMATION, Theory and Practice". Chapters 4-7. McGraw-Hill Companies - 1994
2. Antun Domic, Digital Equipment Corporation, Hudson,"Layout Synthesis of MOS Digitial Cells", DAC 1990
3. Chong-Leong, Ong Jeong-Tyng Li, Chi-Yuan Lo, 26th ACM/IEEE Design Automation Conference,"GENAC: An Automatic Cell Synthesis Tool"
4. Sabyasachi S., Sornavalli R., Dibyendu G., Biswadeep C., "Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies", VLSI Conference, 2001 Bangalore.
5. Kirkpatrik, C.D. Gelatt Jr and M.P. Vechhi, May 1983;"Optimization by Simulated Annealing", Science, Vol.220, No.4598, pp.671-680
6. Carl Sechen, "VLSI Placement and Global Routing Using Simulated Annealing",Kluwer Academic Publishers, 1988
7. Qinghong Wu and Thomas H. Sloane "CMOS Leaf-Cell Design Using Simulated Annealing", IEEE 1992
8. th ACM/IEEE Design Automation Conference
9. Jon Levi,"Dreaming Up a New Methodology for Physical Migration of Hard IP", ISD Mag, May 1999