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Volumn , Issue , 2000, Pages 53-57

Layout-oriented synthesis of high performance analog circuits

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUIT SIZING; CIRCUIT SIZING; LAYOUT GENERATIONS; LAYOUT PARASITICS; OVERALL DESIGN; PHYSICAL LAYOUT;

EID: 11144241239     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840015     Document Type: Conference Paper
Times cited : (25)

References (10)
  • 1
    • 0026118974 scopus 로고
    • KOAN/ANAGRAM II: New tools for device-level analog placement and routing
    • Mar
    • J. M. Cohn, R. A. Rutenbar, and L. R. Carley. KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing. IEEE J. of Solid-State Circuits, 26(3):330-342, Mar. 1991.
    • (1991) IEEE J. of Solid-State Circuits , vol.26 , Issue.3 , pp. 330-342
    • Cohn, J.M.1    Rutenbar, R.A.2    Carley, L.R.3
  • 3
    • 0023600337 scopus 로고
    • Idac: An interactive design tool for analog CMOS circuits
    • Dec
    • M. G. R. Degrauwe and et al. IDAC: An Interactive Design Tool for Analog CMOS Circuits. IEEE J. of Solid-State Circuits, 22(6):1106-1115, Dec. 1987.
    • (1987) IEEE J. of Solid-State Circuits , vol.22 , Issue.6 , pp. 1106-1115
    • Degrauwe, M.G.R.1
  • 4
    • 0029345604 scopus 로고
    • A performance- driven placement tool for analog integrated circuits
    • July
    • K. Lampaert, G. Gielen, andW. M. Sansen. A Performance- Driven Placement Tool for Analog Integrated Circuits. IEEE J. of Solid-State Circuits, 30(7):773-780, July 1995.
    • (1995) IEEE J. of Solid-State Circuits , vol.30 , Issue.7 , pp. 773-780
    • Lampaert, K.1    Gielen, G.2    Sansen, W.M.3
  • 6
    • 0029220994 scopus 로고
    • Optimum CMOS stack generation with analog constraints
    • Jan
    • E. Malavasi and D. Pandini. Optimum CMOS Stack Generation with Analog Constraints. IEEE Trans. Computer-Aided Design, 14(1):107-122, Jan. 1995.
    • (1995) IEEE Trans. Computer-Aided Design , vol.14 , Issue.1 , pp. 107-122
    • Malavasi, E.1    Pandini, D.2
  • 8
    • 0025414530 scopus 로고
    • Operational- amplifier compilation with performance optimization
    • Apr
    • H. Onodera, H. Kanbara, and K. Tamaru. Operational- Amplifier Compilation with Performance Optimization. IEEE J. of Solid-State Circuits, 25(2):466-473, Apr. 1990.
    • (1990) IEEE J. of Solid-State Circuits , vol.25 , Issue.2 , pp. 466-473
    • Onodera, H.1    Kanbara, H.2    Tamaru, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.