Stress-induced voiding and its geometry dependency characterization

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 156-160

  Doong, Kelvin Y Y ^a,b   Wang, Robin C J ^a,b   Lin, S C ^a,b   Hung, L J ^a,b   Lee, S Y ^a,b   Chiu, C C ^a,b   Su, David ^a,b   Wu, Kenneth ^a,b   Young, K L ^a,b   Peng, Y K ^a,b  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b Science based Industrial Park   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODEPOSITION; RELIABILITY; STRESS ANALYSIS; X RAY DIFFRACTION ANALYSIS;

STRESS INDUCED VOIDING (SIV);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0037972839     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. P. Borgesen, J.K. Lee, R. Gleixner, and C.-Y. Li, "Thermal-tress-induced voiding in narrow, passivated Cu line", Appl. Phys. Lett. Vol. 60, pp.1706-1708, 1992
2. A. Wikström, and P. Gudmundson, "Analysis of average thermal stress in passivated metal interconnects", J. Appl. Phys. Vol. 86, pp.6088-6095, 1999
3. Dongwen Gan, Guotao Wang, and Paul S. Ho, "Effects of dielectric material and linewidth on thermal stress of Cu line structures", Proc. Inter. Interconnect Conf., pp.271-273, 2002
4. T. Oshima, T. Tamaru, K. Ohmori, H.Aoki, H. Ashihara, T. Saito, H. Yamaguchi, M. Miyauchi, K. Torii, J. Murata, A. Satoh, H. Miyazaki and K. Hinode, "Improvement of thermal stability of via resistance in dual damascene copper interconnection", IEDM Technical Digest, 2000, pp.123-126
5. Byung-Lyul Park, Sang-Rok Hah, Chan-Geun Park, Dong-Kwon Jeong, Hong-Seong Son, Hyeok-Sang Oh, Ju-Hyuk Chung, Jeong-Lim Nam, Kwang-Myeon Park and Jae-Dong Byun, "Mechanisms of stress-induced voids in multi-level Cu interconnects", Proc. Inter. Interconnect Conf., pp.130-132, 2002
6. M. Ueki, M. Hiroi, N. Ikarashi, T. Onodera, N. Furutake, M. Yoshiki and Y. Hayashi, "Suppression of Stress Induced Open Failures between Via and Cu Wide Line by inserting Ti Layer under Ta/TaN Barrier", IEDM Technical Digest, 2002
7. Norio Okada, Yoshihisa Matsubara, Hidekazu Kimura, Hirokazu Aizawa, Norio Nakamura, "Thermal Stress of 140 nm-width Cu damascene interconnects", Proc. Inter. Interconnect Conf., pp.136-138, 2002
8. T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T.Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama, T. Iwasaki, "Suppression of Stress-Induced Voiding in Copper Interconnects', IEDM Technical Digest, 2002
9. K. Yoshida, T. Fujimaki, K. Miyamoto, T. Honma, H. Kaneko, H. Nakazawa, and M. Morita, "Stress-Induced Voiding Phenomena for an actual CMOS LSI Interconnects", IEDM Technical Digest, 2002
10. E.T. Ogawa, J.W. McPherson, J.A. Rosal, K.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, "Stress-induced voiding under vias connected to wide Cu metal leads", Proc. 2002 IEEE Inter. Reliability Physics Symposium 40 th Annual, pp. 312-321, 2002
11. Kelvin Y.-Y. Doong, L.-J. Hung, Susan Ho, and K.L.Young, "Library-based process test vehicle design framework", to be published in SPIE-2003
12. K.L. Young, S.Y. Wu, C.C. Wu, C.H. Wang, C.T. Lin, J.Y. Cheng, M. Chiang, S.H. Chen, T.C. Lo, Y.S. Chen, J.H. Chen, L.J. Chen, S.Y. Hou, J.J. Liaw, I.E. Chang, C.S. Hou, J. Shih, S.M. Jeng, H.C. Hsieh, Y. Ku, T. Yen, H. Tao, L.C. Chao, S. Shue, S. M.Jang, T.C. Ong, C.H. Yu, M.S. Liang, C.H. Diaz, J.Y.C. Sun, "A 0.13 μ m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications", IEDM Technical Digest, 2000, p. 563-56