On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 1079-1088

  Tang, Huaxing ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMPRESSION; DATA REDUCTION; FLIP FLOP CIRCUITS; SEMICONDUCTOR SWITCHES; SHIFT REGISTERS;

DATA DECOMPRESSION;

INTEGRATED CIRCUIT TESTING;

EID: 0142184748     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

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