-
4
-
-
0024122729
-
Internal chip ESD phenomena beyond the protection circuit
-
Dec.
-
C. Duvvury, R. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. Electron Devices, vol. ED-35, pp. 2133-2139, Dec. 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.ED-35
, pp. 2133-2139
-
-
Duvvury, C.1
Rountree, R.2
Adams, O.3
-
6
-
-
0027702157
-
Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress
-
Nov.
-
H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress," IEEE Trans. Electron Devices, vol. 40, pp. 2081-2083, Nov. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 2081-2083
-
-
Terletzki, H.1
Nikutta, W.2
Reczek, W.3
-
7
-
-
0027882751
-
Two unusual HBM ESD failure mechanisms on a mature CMOS process
-
C. Johnson, T. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," in Proc. EOS/ESD Symp., 1993, pp. 225-231.
-
(1993)
Proc. EOS/ESD Symp.
, pp. 225-231
-
-
Johnson, C.1
Maloney, T.2
Qawami, S.3
-
9
-
-
0042698715
-
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
-
M.-D. Ker, C.-Y. Chang, and Y.-S. Chang, "ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins," in Proc. IEEE Int. ASIC/SOC Conf., 2002, pp. 234-238.
-
(2002)
Proc. IEEE Int. ASIC/SOC Conf.
, pp. 234-238
-
-
Ker, M.-D.1
Chang, C.-Y.2
Chang, Y.-S.3
-
10
-
-
0032740282
-
SS ESD clamp circuits for submicron CMOS VLSI
-
Jan.
-
SS ESD clamp circuits for submicron CMOS VLSI," IEEE Trans. Electron Devices, vol. 46, pp. 173-183, Jan. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 173-183
-
-
Ker, M.-D.1
-
11
-
-
0024174395
-
ESD protection for submicron CMOS circuits: Issues and solutions
-
R. Rountree, "ESD protection for submicron CMOS circuits: Issues and solutions," in IEDM Tech. Dig., 1988, pp. 580-583.
-
(1988)
IEDM Tech. Dig.
, pp. 580-583
-
-
Rountree, R.1
-
12
-
-
0032273088
-
Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: An overview
-
M.-D. Ker, "Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: an overview," in Proc. IEEE Int. Conf. Electronics Circuits and Systems, 1998, pp. 325-328.
-
(1998)
Proc. IEEE Int. Conf. Electronics Circuits and Systems
, pp. 325-328
-
-
Ker, M.-D.1
-
13
-
-
0025953251
-
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
-
Jan.
-
A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, pp. 21-22, Jan. 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 21-22
-
-
Chatterjee, A.1
Polgreen, T.2
-
14
-
-
0030128946
-
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
-
Apr.
-
M.-D. Ker, C.-Y. Wu, and H.-H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, pp. 588-598, Apr. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 588-598
-
-
Ker, M.-D.1
Wu, C.-Y.2
Chang, H.-H.3
-
15
-
-
0030836964
-
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
-
Jan.
-
M.-D. Ker, H.-H. Chang, and C.-Y. Wu, "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 38-51, Jan. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 38-51
-
-
Ker, M.-D.1
Chang, H.-H.2
Wu, C.-Y.3
-
16
-
-
84948982831
-
GGSCR: GGNMOS triggered silicon-controlled rectifiers for ESD protection in deep submicron CMOS processes
-
C. Russ, M. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and K. Verhaege, "GGSCR: GGNMOS triggered silicon-controlled rectifiers for ESD protection in deep submicron CMOS processes," in Proc. EOS/ESD Symp., 2001, pp. 22-31.
-
(2001)
Proc. EOS/ESD Symp.
, pp. 22-31
-
-
Russ, C.1
Mergens, M.2
Armer, J.3
Jozwiak, P.4
Kolluri, G.5
Avery, L.6
Verhaege, K.7
-
17
-
-
0027883867
-
ESD protection of BiCMOS integrated circuits which need to operate in the harsh environments of automotive or industrial
-
M. Corsi, R. Nimmo, and F. Fattori, "ESD protection of BiCMOS integrated circuits which need to operate in the harsh environments of automotive or industrial," in Proc. EOS/ESD Symp., 1993, pp. 209-213.
-
(1993)
Proc. EOS/ESD Symp.
, pp. 209-213
-
-
Corsi, M.1
Nimmo, R.2
Fattori, F.3
-
18
-
-
0031249221
-
Using an SCR as ESD protection without latch-up danger
-
G. Notermans, F. Kuper, and J. M. Luchis, "Using an SCR as ESD protection without latch-up danger," Microelectron. Reliabil., vol. 37, pp. 1457-1460, 1997.
-
(1997)
Microelectron. Reliabil.
, vol.37
, pp. 1457-1460
-
-
Notermans, G.1
Kuper, F.2
Luchis, J.M.3
-
19
-
-
0011003950
-
Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology
-
Apr.
-
M.-D. Ker, "Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology," IEEE Trans. Electron Devices, vol. 45, pp. 849-860, Apr. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, pp. 849-860
-
-
Ker, M.-D.1
-
20
-
-
0032309711
-
How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on
-
M.-D. Ker and H.-H. Chang, "How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on," in Proc. EOS/ESD Symp., 1998, pp. 72-85.
-
(1998)
Proc. EOS/ESD Symp.
, pp. 72-85
-
-
Ker, M.-D.1
Chang, H.-H.2
-
21
-
-
0036287788
-
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
-
M.-D. Ker and K.-C. Hsu, "On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process," in Proc. IEEE Int. Symp. Circuits and Systems, 2002, pp. 529-532.
-
(2002)
Proc. IEEE Int. Symp. Circuits and Systems
, pp. 529-532
-
-
Ker, M.-D.1
Hsu, K.-C.2
-
22
-
-
79956346072
-
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
-
_, "Complementary substrate-triggered SCR devices for on-chip ESD protection circuits," in Proc. IEEE Int. ASIC/SOC Conf., 2002, pp. 229-233.
-
(2002)
Proc. IEEE Int. ASIC/SOC Conf.
, pp. 229-233
-
-
-
23
-
-
0009558710
-
Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method - Part I: Theoretical derivation
-
June
-
M.-D. Ker and C.-Y. Wu, "Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method - Part I: Theoretical derivation," IEEE Trans. Electron Devices, vol. 42, pp. 1141-1148, June 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 1141-1148
-
-
Ker, M.-D.1
Wu, C.-Y.2
-
25
-
-
0030242764
-
Capacitor-coupled ESD protection circuit for deep-submicron low-voltage CMOS ASIC
-
Sept.
-
M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, "Capacitor-coupled ESD protection circuit for deep-submicron low-voltage CMOS ASIC," IEEE Trans. VLSI Syst., vol. 4, pp. 307-321, Sept. 1996.
-
(1996)
IEEE Trans. VLSI Syst.
, vol.4
, pp. 307-321
-
-
Ker, M.-D.1
Wu, C.-Y.2
Cheng, T.3
Chang, H.-H.4
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