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Volumn 43, Issue 4, 1996, Pages 588-598

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Author keywords

[No Author keywords available]

Indexed keywords

ACCIDENT PREVENTION; ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTRIC LINES; HIGH TEMPERATURE EFFECTS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; PROTECTION; THYRISTORS; VLSI CIRCUITS;

EID: 0030128946     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.1996.1210725     Document Type: Article
Times cited : (51)

References (15)
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    • Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins
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    • Ker, M.-D.1
  • 3
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    • A low-voltage triggering SCR for onchip ESD protection at output and input pads
    • A. Chatterjee T. Polgreen A low-voltage triggering SCR for onchip ESD protection at output and input pads IEEE Electron Device Lett. 12 1 21 22 Jan. 1991
    • (1991) IEEE Electron Device Lett. , vol.12 , Issue.1 , pp. 21-22
    • Chatterjee, A.1    Polgreen, T.2
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    • A synthesis of ESD input protection scheme
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    • , vol.EOS-13 , pp. 88-97
    • Duvvury, C.1    Rountree, R.2
  • 5
    • 0024122729 scopus 로고
    • Internal chip ESD phenomena beyond the protection circuit
    • C. Duvvury R. N. Rountree O. Adams Internal chip ESD phenomena beyond the protection circuit IEEE Trans. Electron Devices 35 12 2133 2139 Dec. 1988
    • (1988) IEEE Trans. Electron Devices , vol.35 , Issue.12 , pp. 2133-2139
    • Duvvury, C.1    Rountree, R.N.2    Adams, O.3
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    • Characterization of new failure mechanisms arising from power-pin ESD stressing
    • C. Cook S. Daniel Characterization of new failure mechanisms arising from power-pin ESD stressing Proc. 1993 EOS/ESD Symp. EOS-15 149 156 Proc. 1993 EOS/ESD Symp.
    • , vol.EOS-15 , pp. 149-156
    • Cook, C.1    Daniel, S.2
  • 7
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    • Electrostatic discharge protection in a 4-Mbit DRAM
    • M. D. Jaffe P. E. Cottrell Electrostatic discharge protection in a 4-Mbit DRAM Proc. 1990 EOS/ESD Symp. EOS-12 218 223 Proc. 1990 EOS/ESD Symp.
    • , vol.EOS-12 , pp. 218-223
    • Jaffe, M.D.1    Cottrell, P.E.2
  • 8
    • 0027882751 scopus 로고    scopus 로고
    • Two unusual HBM ESD failure mechanisms on a mature CMOS process
    • C. C. Johnson T. J. Maloney S. Qawami Two unusual HBM ESD failure mechanisms on a mature CMOS process Proc. 1993 EOS/ESD Symp. EOS-15 225 231 Proc. 1993 EOS/ESD Symp.
    • , vol.EOS-15 , pp. 225-231
    • Johnson, C.C.1    Maloney, T.J.2    Qawami, S.3
  • 9
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    • Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress
    • H. Terletzki W. Nikutta W. Reczek Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress IEEE Trans. Electron Devices 40 II 2081 2083 Nov. 1993
    • (1993) IEEE Trans. Electron Devices , vol.40 , Issue.II , pp. 2081-2083
    • Terletzki, H.1    Nikutta, W.2    Reczek, W.3
  • 10
    • 0029204489 scopus 로고    scopus 로고
    • Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's
    • M.-D. Ker C.-Y. Wu H.-H. Chang T. Cheng T.-S. Wu Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's Proc. 1995 IEEE Int. Symp. Circuits and Systems 833 836 Proc. 1995 IEEE Int. Symp. Circuits and Systems
    • Ker, M.-D.1    Wu, C.-Y.2    Chang, H.-H.3    Cheng, T.4    Wu, T.-S.5
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    • Voldman, S.H.1    Gerosa, G.2
  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.