How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1998, Pages 72-85

  Ker, Ming Dou ^a   Chang, Hun Hsien ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT;

ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS;

ELECTRIC SHIELDING;

EID: 0032309711     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (42)