On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Ker, Ming Dou ^a   Hsu, Kuo Chun ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTROSTATICS; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE STRUCTURES; STRESSES; THYRISTORS;

ELECTROSTATIC DISCHARGE; HUMAN BODY MODEL; SUBSTRATE-TRIGGERED METHOD;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287788     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. ESD protection for submicron CMOS circuits: Issues and solutions
2. A synthesis of ESD input protection scheme
3. A low-voltage triggering SCR for on-chip ESD protection at output and input pads
4. Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's
5. A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
6. ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique
7. Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology
8. Transient-induced latchup testing of CMOS integrated circuits
9. Antenna protection strategy for ultra-thin gate MOSFETs