Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 229-233

  Ker, Ming Dou ^a   Hsu, Kuo Chun ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DIODES; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; VOLTAGE CONTROL;

CMOS PROCESSS; ESD LEVEL; ESD PROTECTION CIRCUIT; ESD STRESS; HOLDING VOLTAGE; LAYOUT AREA; ON-CHIP ESD PROTECTION; TRANSIENT-INDUCED LATCHUP;

SUBSTRATES;

EID: 79956346072     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158061     Document Type: Conference Paper

References (9)

1. R. Rountree, "ESD protection for submicron CMOS circuits: issues and solutions," in IEDM Tech. Dig., 1988, pp. 580-583.
2. M.-D. Ker, "Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overvies," Proc. of IEEE Int. Conf. on Electronics Circuits and Systems, 1998, pp. 325-328.
3. A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device letters, vol. 12, pp. 21-22, 1991.
4. M.-D. Ker, et al., "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans, on Electron Devices, vol. 43, no. 4, pp. 588-598,1996.
5. M.-D. Ker, et al., "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's," IEEE Journal of Solid-State Circuits, vol. 32, pp. 38-51, 1997.
6. C. Russ, et al., "GGSCR:GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes," in Proc. of EOS/ESD Symp., 2001, pp. 22-31.
7. M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, "ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique," in Proc. of IEEE int. Symp. on Circuits and Systems, 2001, vol. 4, pp. 754-757.
8. M.-D. Ker, et al, "How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on," in Proc. of EOS/ESD Symp., 1998, pp. 72-85.
9. S. Krishnan and A. Amerasekera, "Antenna protection strategy for ultra-thin gate MOSFETs," in Proc. of IEEE Int. Reliability Physics Symp. 1998, pp. 302-306.