Simultaneous peak and average power minimization during datapath scheduling for DSP processors

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 215-220

  Mohanty, Saraju P ^a   Ranganathan, N ^a   Chappidi, Sunil K ^a  

^a University of South Florida   (United States)

Author keywords

Average Power; Datapath Scheduling; Dynamic Frequency Clocking; High level Synthesis; Multiple Voltages; Peak power

Indexed keywords

ALGORITHMS; COMPUTER CIRCUITS; COMPUTER PROGRAMMING; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; POWER ELECTRONICS;

DATAPATH SCHEDULING;

DIGITAL SIGNAL PROCESSING;

EID: 0038714049     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764863.764864     Document Type: Conference Paper

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