Peak power minimization through datapath scheduling

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 121-126

  Mohanty, Saraju P ^a   Ranganathan, N ^a   Chappidi, Sunil K ^a  

^a University of South Florida   (United States)

Author keywords

Circuits; Clocks; Delay effects; Delay estimation; Energy consumption; Frequency; Integer linear programming; Minimization; Scheduling algorithm; Voltage

Indexed keywords

ALGORITHMS; CLOCKS; DELAY CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; FLOW MEASUREMENT; FREQUENCY ESTIMATION; HIGH LEVEL SYNTHESIS; INTEGER PROGRAMMING; NETWORKS (CIRCUITS); OPTIMIZATION; SCHEDULING; VLSI CIRCUITS;

DELAY EFFECTS; DELAY ESTIMATION; FREQUENCY; INTEGER LINEAR PROGRAMMING; INTEGER LINEAR PROGRAMMING MODELS; MULTIPLE SUPPLY VOLTAGES; PEAK POWER MINIMIZATIONS; PEAK POWER REDUCTION;

SCHEDULING ALGORITHMS;

EID: 84942048053     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183362     Document Type: Conference Paper

References (14)

1. L. Benini, E. Macii, M. Pnocino, and G. D. Micheli. Telescopic units : A new paradigm for performance optimization of VLSI design. IEEE Trans. on CAD, 17(3):220-232, Mar 1998.
2. I. Brynjolfson and Z. Zilic. Dynamic clock management for low power applications in FPGAs. In Proc. of IEEE Custom Integrated Circuits Conference, pages 139-142, 2000.
3. J. M. Chang and M. Pedram. Energy minimization using multiple supply voltages. IEEE Trans. on VLSI Systems, 5(4):436-443, Dec 1997.
4. M. Johnson and K. Roy. Datapath scheduling with multiple supply voltages and level converters. ACM Trans. on Design Automation of Electronic Systems, 2(3):227-248, July 1997.
5. Y. R. Lin, C. T. Hwang, and A. C. H. Wu. Scheduling techniques for variable voltage low power design. ACM Trans. on Design Automation of Electronic Systems, 2(2):81-97, Apr 1997.
6. R. S. Martin and J. P. Knight. Using spice and behavioral synthesis tools to optimize ASICs' peak power consmpution. In Proc. of 38th Midwest Symposium on Circuits and Systems, pages 1209-1212, 1996.
7. S. P. Mohanty and N. Ranganathan. Energy efficient scheduling for datapath synthesis. In Proc. of Intl. Conf. on VLSI Design (to appear), Jan 2003.
8. S. P. Mohanty, N. Ranganathan, and V. Krishna. Datapath scheduling using dynamic frequency clocking. In Proc. of ISVLSI'2002, pages 65-70, Apr 2002.
9. S. Park and K. Choi. Performance-driven high-level synthesis with bit-level chaining and clock selection. IEEE Trans. on CAD, 20(2):199-212, Feb 2001.
10. V. Raghunathan, S. Ravi, A. Raghunathan, and G. Lakshminarayana. Transient power management through high level synthesis. In Proc. of ICCAD, pages 545-552, 2001.
11. N. Ranganathan, N. Vijaykrishnan, and N. Bhavanishankar. A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. on CSVT, 8(4):435-445, August 1998.
12. W. T. Shiue. High level synthesis for peak power minimization using ILP. In Proc. of IEEE International Conference on Application Specific Systems, Architectures and Processors, pages 103-112, 2000.
13. W. T. Shiue and C. Chakrabarti. ILP based scheme for low power scheduling and resource binding. In Proc. of ISCAS, pages III.279-III.282, 2000.
14. D. Singh, J. M. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. J. Mozdzen. Power conscious cad tools and methodologies: A perspective. Proceedings of the IEEE, 83(4):570-594, Apr 1995.