Performance-driven high-level synthesis with bit-level chaining and clock selection

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 2, 2001, Pages 199-212

  Park, Sanghun ^b   Choi, Kiyoung ^a,c  

^a IEEE

^b Hynix Semiconductor Inc   (South Korea)

^c Seoul National University   (South Korea)

Author keywords

Bit level chaining; Control synthesis; High level synthesis; Scheduling; System clock optimization

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; CONTROL SYSTEM SYNTHESIS; FINITE AUTOMATA; OPTIMIZATION; RESOURCE ALLOCATION;

BIT LEVEL CHAINING; CLOCK SELECTION; HIGH LEVEL SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035248154     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.908436     Document Type: Article

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