Coping with buffer delay change due to power and ground noise

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 860-865

  Chen, Lauren Hui ^a   Marek Sadowska, Malgorzata ^b   Brewer, Forrest ^b  

^a SYNOPSYS INC   (United States)

^b University of California   (United States)

Author keywords

Common mode noise; Differential mode noise; Incremental delay change; Power and ground noise

Indexed keywords

DIFFERENTIAL MODE NOISE;

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER AIDED ENGINEERING; ELECTRONICS PACKAGING; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION REPEATERS; TIMING JITTER; TRANSISTORS;

VLSI CIRCUITS;

EID: 0036045515     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012742     Document Type: Article

References (12)

1. Buffer insertion for noise and delay optimization
2. CMOS gate delay models for general RLC loading
3. Interconnect and circuit modeling techniques for full-chip power supply norse analysis
4. CMOS circuit speed and buffer optimization
5. Analysis and optimization of ground bounce in digital CMOS circuits
6. Estimation of ground bounce effects on CMOS circuits
7. Optimal wire sizing and buffer insertion for low power and a generalized delay model
8. Modeling the "effective capacitance" for the RC interconnect of CMOS gates
9. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
10. Clock skew verification in the presence of IR-drop in the power distribution network
11. Effects of simultaneous switching noise on the tapered buffer design
12. Design for velocity saturated, short- channel CMOS drivers with simultaneous switching noise and switching time considerations