An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 68-73

  Su, Haihua ^a   Sapatnekar, Sachin S ^a   Nassif, Sani R ^a  

^a IBM   (United States)

Author keywords

Adjoint sensitivity; ASICs; Decoupling capacitor; Optimization; Placement; Power grid noise

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITORS; DEGREES OF FREEDOM (MECHANICS); NATURAL FREQUENCIES; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

DEOUPLING CAPACITORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036374252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505401.505405     Document Type: Conference Paper

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