Clock skew verification in the presence of IR-drop in the power distribution network

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 6, 2000, Pages 635-644

  Saleh, Resve ^a   Hussain, Syed Zakir ^a   Rochel, Steffen ^a   Overhauser, David ^a  

^a Simplex Solutions Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ITERATIVE METHODS; VLSI CIRCUITS;

CLOCK SKEW; DEEP SUBMICROMETER DIGITAL CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTIONS; MATRIX DECOMPOSITION; POWER DISTRIBUTION NETWORK; POWER GRID VOLTAGE DROP; RELAXATION METHODS; SOFTWARE PACKAGE SPICE;

TIMING CIRCUITS;

EID: 0033689265     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.848085     Document Type: Article

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