A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 7, 2003, Pages 1213-1219

  Song, Seong Jun ^a   Park, Sung Min ^b   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b University of Ulsan   (South Korea)

Author keywords

1 8 rate clock; Clock and data recovery; CMOS; Linear phase detector; Optical receivers; Voltage controlled oscillator (VCO)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA REDUCTION; SIGNAL RECEIVERS; VARIABLE FREQUENCY OSCILLATORS;

DATA RECOVERY CIRCUITS;

TIMING CIRCUITS;

EID: 0038155581     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.813292     Document Type: Article

References (24)

1. W.-H. Chen, G.-K. Dehng, J.-W. Chen, and S.-I. Liu, "A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme," IEEE J. Solid-State Circuits, vol. 36, pp. 1498-1505, Dec. 1995.
2. G. W. den Besten, "Embedded low-cost 1.2 Gb/s inter-IC serial data link in 0.35-μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 250-251.
3. D. Friedman, M. Meghelli, B. Parker, J. Yang, H. Ainspan, and M. Soyuer, "A single-chip 12.5 Gbaud transceiver for serial data communication," in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 145-148.
4. N. Ishihara, S. Fujita, M. Togashi, S. Hino, Y. Arai, N. Tanaka, Y. Kobayashi, and Y. Akazawa, "3.5-Gb/s × 4-Ch Si bipolar LSI's for optical interconnections," IEEE J. Solid-State Circuits, vol. 30, pp. 1493-1501, Dec. 1995.
5. J. Yang, J. Choi, D. M. Kuchta, K. G. Stawiasz, P. Pepeljugoski, and H. A. Ainspan, "A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology," IEEE J. Solid-State Circuits, vol. 30, pp. 2197-2204, Dec. 1998.
6. J. Lee, S.-J. Song, S. M. Park, C.-M. Nam, Y.-S. Kwon, and H.-J. Yoo, "A multichip on oxide of 1G b/s 80 dBΩ fully-differential CMOS transimpedance amplifier for optical interconnect applications," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 80-81.
7. S. M. Park and C. Toumazou, "A packaged low-noise high-speed regulated cascode transimpedance amplifier using a 0.6-μm N-well CMOS technology," in Proc. Eur. Solid State Circuits Conf., Sept. 2000, pp. 432-435.
8. S. M. Park and H.-J. Yoo, "2.5-Gb/s CMOS transimpedance amplifier for optical communication applications," Electron. Lett., vol. 39, pp. 211-212, Jan. 2003.
9. A. Tanabe, M. Soda, Y. Nakahara, T. Tamura, K. Yoshida, and A. Furukawa, "A single-chip 2:4-Gb/s CMOS optical receiver with low substrate cross-talk preamplifier," IEEE J. Solid-State Circuits, vol. 33, pp. 2148-2153, Dec. 1998.
10. T. Yoshimura, K. Ueda, J. Takasoh, Y. Wada, T. Oka, H. Kondoh, O. Chiba, Y. Azekawa, and M. Ishiwaki, "A 10 Gbase ethernet transceiver (LAN PHY) in a 1.8 V. 0.18 um SOI/CMOS technology," in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 355-358.
11. M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, "SiGe BiCMOS 3.3 V clock and data recovery circuits for 10 Gb/s serial transmission systems," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 56-57.
12. t silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 34, pp. 1320-1324, Sept. 1999.
13. M. Reinhold, C. Dorschky, E. Rose, R. Pullela, P. Mayer, F. Kunz, Y. Baeyens, T. Link, and J.-P. Mania, "A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology," IEEE J. Solid-State Circuits, vol. 36, pp. 1937-1945, Dec. 2001.
14. K. Ishii, H. Nosaka, H. Nakajima, K. Kurishima, M. Ida, N. Watanabe, Y. Yamane, E. Sano, and T. Enoki, "Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors," IEEE J. Solid-State Circuits, vol. 37, pp. 1146-1151, Sept. 2002.
15. A. Mointaz, J. Cao, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, W.-G. Tan, K.-C. Jen, I. Fujimori, and Y. Cai, "A fully integrated SONET OC-48 transceiver in standard CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1964-1973, Dec. 2001.
16. M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer, and N. Menoux, "Clock/data recovery PLL using half-frequency clock," IEEE J. Solid-State Circuits, vol. 32, pp. 1156-1159, July 1997.
17. J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector," IEEE J. Solid-State Circuits, vol. 36, pp. 761-767, May 2001.
18. H.-J. Yoo, "Gigabit throughput CMOS IC's for optical interconnection applications," in Ext. Abst. Solid State Devices and Materials Conf., Sept. 2002, pp. 252-253.
19. C.-K. K. Yang, R. Farjad-Rad, and M. Horowitz, "A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling," IEEE J. Solid-State Circuits, vol. 33, pp. 713-722, May 1998.
20. M. Fukaishi, K. Nakamura, M. Sato, Y. Tsutsui, S. Kishi, and M. Yotsuyanagi, "A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture," IEEE J. Solid-State Circuits, vol. 33, pp. 2139-2147, Dec. 1998.
21. M. van Heijningen, M. Badaroglu, S. Donnay, G. G. E. Gielen, and H. J. De Man, "Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification," IEEE J. Solid-State Circuits, vol. 37, pp. 1065-1072, Aug. 2002.
22. K. Pedrotti, "High speed circuits for lightwave communications," Int. J. High Speed Electron. Syst., vol. 9, pp. 313-346, 1998.
23. J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, Aug. 2000.
24. C. R. Hogge, "A self correcting clock recovery circuit," J. Lightwave Technol., vol. LT-3, pp. 1312-1314, Dec. 1985.