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Volumn 34, Issue 9, 1999, Pages 1320-1324

A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz fT Silicon Bipolar Technology

Author keywords

Bipolar digital integrated circuits; Clocks; Data communication; High speed integrated circuits; Phase locked loops; Synchronization

Indexed keywords


EID: 0348099745     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.782092     Document Type: Article
Times cited : (33)

References (14)
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  • 2
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  • 3
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    • 20 Gbit/s TDM nonrepeatered transmission over 198 km DSF using Si-bipolar IC for demultiplexing and clock recovery
    • Sept. paper TuD.3.4
    • W. Bogner, U. Fischer, E. Gottwald, and E. Müllner, "20 Gbit/s TDM nonrepeatered transmission over 198 km DSF using Si-bipolar IC for demultiplexing and clock recovery," in Proc. ECOC, Sept. 1996, paper TuD.3.4.
    • (1996) Proc. ECOC
    • Bogner, W.1    Fischer, U.2    Gottwald, E.3    Müllner, E.4
  • 4
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    • Dec.
    • W. Bogner, E. Gottwald, A. Schöpflin, and C.-J. Weiske, "40 Gbit/s unrepeatered optical transmission over 148 km by electrical time division multiplexing and demultiplexing," Electron. Lett., vol. 33, no. 25, pp. 2136-2137, Dec. 1997.
    • (1997) Electron. Lett. , vol.33 , Issue.25 , pp. 2136-2137
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  • 8
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    • 60 Gbit/s regenerating demultiplexer in SiGe bipolar technology
    • Nov.
    • A. Felder, M. Möller, M. Wurzer, M. Rest, T. F. Meister, and H.-M. Rein, "60 Gbit/s regenerating demultiplexer in SiGe bipolar technology." Electron. Lett., vol. 33, no. 23, pp. 1984-1986, Nov. 1997.
    • (1997) Electron. Lett. , vol.33 , Issue.23 , pp. 1984-1986
    • Felder, A.1    Möller, M.2    Wurzer, M.3    Rest, M.4    Meister, T.F.5    Rein, H.-M.6
  • 9
    • 84939378388 scopus 로고
    • A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology
    • Sept.
    • J. Hauenschild, A. Felder, M. Kerber, H.-M. Rein, and L. Schmidt, "A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology," in Proc. IEEE BCTM' 92, Sept. 1992, pp. 151-154.
    • (1992) Proc. IEEE BCTM' 92 , pp. 151-154
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  • 10
    • 0030213937 scopus 로고    scopus 로고
    • Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s
    • Aug.
    • H.-M. Rein and M. Möller, "Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s," IEEE J. Solid-State Circuits, vol. 31, pp. 1076-1090, Aug. 1996.
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  • 11
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  • 13
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    • J. Böck, M. Franosch, H. Schäfer, H. v. Philipsborn, and J. Popp, "In-situ doped emitter-polysilicon for 0.5 μm silicon bipolar technology," in Proc. ESSDERC'95. The Hague, the Netherlands, Sept. 1995, pp. 421-424.
    • (1995) Proc. ESSDERC'95 , pp. 421-424
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.