SiGe BICMOS 3.3V clock and data recovery circuits for 10Gb/s serial transmission systems

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 56-57

  Meghelli, M ^a   Parker, B ^a   Ainspan, H ^a   Soyuer, M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DATA ACQUISITION; JITTER; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION LINKS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY (CDR) CIRCUITS;

DATA COMMUNICATION SYSTEMS;

EID: 0034429692     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A SiGe single-chip 3.3V receiver IC for 10Gb/s optical communication systems
2. SiGe clock and data recovery IC with linear type PLL for 10Gb/s SONET application
3. A 10Gb/s Si-Bipolar TX/RX chipset for computer data transmission