A novel strategy to test core based designs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 122-127

  Bagchi, Debabrata ^a   Chowdhury, Dipanwita Roy ^a   Mukherjee, Joy ^a   Chattopadhyay, Shantanu ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; OPTIMIZATION;

TEST ACCESS MECHANISM (TAM);

DESIGN FOR TESTABILITY;

EID: 0035017973     PISSN: 10639667     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICVD.2001.902650     Document Type: Article

References (0)