Polynomial-time algorithm for power constrained testing of core based systems

Proceedings of the Asian Test Symposium

Volumn , Issue , 1999, Pages 107-112

  Ravikumar, C P ^a   Verma, Ashutosh ^a   Chandra, Gaurav ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

POLYNOMIAL-TIME ALGORITHMS; SYSTEMS-ON-CHIP (SOC);

ALGORITHMS; CONSTRAINT THEORY; INTEGRATED CIRCUIT TESTING; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; POLYNOMIALS;

BUILT-IN SELF TEST;

EID: 0033357319     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (11)

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