CMOS transistor in nanoscale era

IEICE Transactions on Electronics

Volumn E85-C, Issue 5, 2002, Pages 1052-1056

  Yu, Bin ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

CMOS; Integration; Semiconductor devices; Transistor

Indexed keywords

CARRIER MOBILITY; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; ELECTRIC FIELD EFFECTS; ELECTRON TUNNELING; FABRICATION; GATES (TRANSISTOR); LEAKAGE CURRENTS; NANOTECHNOLOGY; PERFORMANCE; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTOR JUNCTIONS;

CHANNEL DOPANT PROFILE ENGINEERING; GATE DIELECTRICS; GATE TUNNELING LEAKAGE; SALICIDE; SUPER HALO IMPLANT; ULTRA-SHALLOW JUNCTIONS; X;

CMOS INTEGRATED CIRCUITS;

EID: 0036579172     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)

1. + polysilicon-gated ultra-thin oxides (21-26A)
2. Limits of gate-oxide scaling in nano-transistors
3. The ballistic nano-transistor
4. Scaling towards 35 nm gate length CMOS
5. 25 nm CMOS design considerations
6. 70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)
7. 50 nm gate length CMOS transistor with super-halo: Design, process, and reliability
8. Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes
9. 15 nm gate length planar CMOS transistor
10. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
11. Sub-60 nm physical gate length SOI CMOS
12. CMOS device scaling beyond 100 nm
13. 45 nm gate length CMOS technology and beyond using steep halo
14. A 70 nm gate length CMOS technology with 1.0 V operation
15. 100 nm gate length high performance/low power CMOS transistor structure