50nm gate-length CMOS transistor with super-halo: design, process, and reliability

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 653-656

  Yu, Bin ^a   Wang, Haihong ^a   Milic, Ognjen ^a   Xiang, Qi ^a   Wang, Weizhong ^a   Xilin An, Judy ^a   Lin, Ming Ren ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR); HOT CARRIERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; OXIDES; RELIABILITY;

BAND TO BAND TUNNELING LEAKAGE; FIGURE OF MERIT; GATE OXIDE LEAKAGE; SUPER HALO;

CMOS INTEGRATED CIRCUITS;

EID: 0033345379     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)