Trends in high-performance, low-power cache memory architectures

IEICE Transactions on Electronics

Volumn E85-C, Issue 2, 2002, Pages 304-314

  Inoue, Koji ^a   Moshnyaga, Vasily G ^a   Murakami, Kazuaki ^b  

^a FUKUOKA UNIVERSITY   (Japan)

^b KYUSHU UNIVERSITY   (Japan)

Author keywords

Cache; High performance; Low power; Microprocessor; Survey

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

CACHE MEMORY ARCHITECTURES;

BUFFER STORAGE;

EID: 0036475888     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (64)

1. Cache performance of operating systems and multiprogramming
2. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches
3. Selective cache ways: On-demand cache resource allocation
4. Instruction buffering to reduce power in processors for signal processing
5. Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors
6. Using dynamic cache management techniques to reduce energy in a high-performance processor
7. Energy and performance improvements in microprocessor design using a loop cache
8. Predictive sequential associative cache
9. Cache design of a submicron CMOS system370
10. Application-specific memory management for embedded systems using software-controlled caches
11. Adjustable block size coherent caches
12. The non-critical buffer: Using load latency tolerance to improve data cache efficiency
13. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
14. A data cache with multiple caching strategies tuned to different types of locality
15. SH3: High code density, low power
16. Achieving high instruction cache performance with an optimizing compiler
17. Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs
18. Way-predicting set-associative cache for high performance and low energy consumption
19. Performance/energy efficiency of variable line-size caches on intelligent memory systems
20. A low-power instruction cache architecture exploiting program execution footprints
21. A power reduction technique with object code merging for application specific embedded processors
22. Design and performance evaluation of a cache assist to implement selective caching
23. Run-time spatial locality detection and optimization
24. Run-time adaptive cache hierarchy management via reference analysis
25. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
26. A 300-MHz 115-W 32-b bipolar ECL microprocessor
27. The difference-bit cache
28. Temporal-based procedure reordering for improved instruction cache performance
29. Analytical energy dissipation models for low power caches
30. Low power technique for onchip memory using biased partitioning and access concentration
31. Cacheline decay: A mechanism to reduce cache leakage power
32. Inexpensive implementations of set-associativity
33. Multiple access caches: Energy implications
34. The filter cache: An energy efficient memory structure
35. Energy optimization of multi-level processor cache architecture
36. Exploiting spatial locality in data caches using spatial footprints
37. Region-based caching: An energy-delay efficient memory architecture for embedded processors
38. Cache design with partial address matching
39. Cache replacement with dynamic exclusion
40. Reducing cache engery through dual voltage supply
41. Parallel processing RAM chip with 256 Mb DRAM and quad processors
42. Software controlled reconfigurable on-chip memory for high performance computing
43. Memory organization for improved data cache performance in embedded processors
44. Efficient utilization of scratch-pad memory in embedded processor applications
45. Reducing the frequency of tag compares for low power I-cache design
46. Intelligent RAM (IRAM) chips that remember and compute
47. Capturing dynamic memory reference behavior with adaptive cache topology
48. Static locality analysis for cache management
49. StrongARM SA110 - A 160MHz 32b 0.5W CMOS ARM processor
50. Missing the memory wall: The case for processor/memory integration
51. Low power design techniques for microprocessors
52. Load latency tolerance in dynamically scheduled processors
53. Cache design trade-offs for power and performance optimization: A case study
54. A design framework for hybrid-access caches
55. Code placement techniques for cache miss rate reduction
56. A modified approach to data cache management
57. Adapting cache line size to application behavior
58. Pursuing the performance potential of dynamic cache line sizes
59. Pollution control caching
60. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches
61. Two fast and high-associativity cache schemes