Reducing cache energy through dual voltage supply

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 302-305

  Moshnyaga, V G ^a  

^a FUKUOKA UNIVERSITY   (Japan)

Author keywords

Banking; Capacitance; Clocks; Design optimization; Energy consumption; Energy dissipation; Microprocessors; Phased arrays; Pipelines; Voltage

Indexed keywords

ANTENNA PHASED ARRAYS; CLOCKS; COMPUTER AIDED DESIGN; DESIGN; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; PIPELINES;

AREA OVERHEAD; BANKING; CLOCK CYCLE TIME; DESIGN OPTIMIZATION; REDUCE ENERGY CONSUMPTION; SUPPLY VOLTAGES; VOLTAGE LEVELS; VOLTAGE SUPPLY;

CAPACITANCE;

EID: 84895256103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913323     Document Type: Conference Paper

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