Energy optimization of multi-level processor cache architectures

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1995, Pages 45-49

  Ko, Uming ^a   Balsara, Poras T ^a   Nanda, Ashwini K ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; OPTIMIZATION; TRANSISTORS;

MULTILEVEL PROCESSOR CACHE ARCHITECTURES;

DATA STORAGE EQUIPMENT;

EID: 0029194648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/224081.224090     Document Type: Conference Paper

References (7)