Complete, contactless I/O testing - Reaching the boundary in minimizing digital IC testing cost

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 446-455

  Sunter, Stephen K ^a   Nadeau Dostie, Benoit ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COST BENEFIT ANALYSIS; DIGITAL INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; IMPEDANCE MATCHING (ELECTRIC); LOGIC DEVICES; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; STANDARDS;

AUTOMATIC TEST EQUIPMENT; DIGITAL INTEGRATED CIRCUIT TESTING; INPUT OUTPUT TESTING; MIXED SIGNAL FUNCTIONS; POWER RAIL IMPEDANCE; TESTING COST;

INTEGRATED CIRCUIT TESTING;

EID: 0036446210     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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