Jitter testing for gigabit serial communication transceivers

IEEE Design and Test of Computers

Volumn 19, Issue 1, 2002, Pages 66-74

  Cai, Yi ^a   Laquai, Bernd ^b   Luehman, Kent ^b  

^a AGERE SYSTEMS   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; DATA COMMUNICATION SYSTEMS; PASSIVE FILTERS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIMING JITTER; TRANSCEIVERS; TRANSFER FUNCTIONS; VARIABLE FREQUENCY OSCILLATORS;

DELAY-LOCKED LOOP (DLL); SERIAL COMMUNICATION;

INTEGRATED CIRCUIT TESTING;

EID: 0036142374     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.980054     Document Type: Article

References (5)

1. Digital serial communication device testing and its implications on automatic test equipment architecture
2. High frequency serial communication: Technology requirement
3. Measuring jitter of high speed data channels using undersampling techniques